The invention relates to CIS technology, and, more particularly, to processes for forming CIS integrated circuits which utilize non-memory field effect transistors (FETs) and passive polysilicon components.
The cost and time required to fabricate CIS microelectronic circuits is related directly to the number of masking steps. Unfortunately, when polysilicon resistors or conductors are used in such circuits, separate masking (and doping) sequences are used to establish the threshold voltage of the field-effect transistors and the resistance of the polysilicon. It is desirable to reduce the number of such steps, for example, by combining the separate masking steps.
The prior art teaches doping one or more active and/or passive circuit components using a single doping step. For example, U.S. Pat. No. 4,075,045 issued Feb. 21, 1978, to Rideout, uses the source and drain diffusion process to simultaneously form a substrate capacitor electrode. U.S. Pat. No. 3,889,358, issued June 17, 1975, to Bierhenke, tailors the threshold voltage of an FET and the resistance of a substrate load resistor of an inverter circuit by simultaneous doping. The resistance of the resistor can very widely, without any serious effect on the performance of the circuit. Thus, the impurity concentration resulting from the doping is unimportant.
U.S. Pat. No. 3,996,657 issued Dec. 14, 1976 to Simko relates to a floating gate, avalanche injected, MOS (metal oxide semiconductor) structure and to a process for doping the source and drain simultaneously with the doping of the polysilicon floating gate or the polysilicon control gate. Simultaneous doping apparently is possible because the doping level for the gate can vary widely, or because the gate has the same doping level requirements as the source and drain.
In U.S. Pat. No. 4,080,718 issued Mar. 28, 1978 to Richman, an FET channel is doped by implantation through a polysilicon gate, which is doped incidentally to the channel doping. In U.S. Pat. No. 3,750,268, issued Sept. 10, 1971 to Wang, source and drain electrodes are apparently doped incidentally to the process of establishing ohmic contact between the source and drain and their respective electrodes.
It is apparent that simultaneous doping of field-effect transistors and polysilicon conductors or resistors to establish the threshold voltage and to establish the conductance or resistance of the polysilicon is highly desirable to the aim of reducing masking steps and, therefore, production costs. It is also apparent that the above patents have achieved advances in the use of implantation and diffusion during MOSFET processing. These patents indicate that various substrate components can be doped simultaneously, and that, where the precise resistance of polysilicon is unimportant, polysilicon components can be doped as a by-product of forming other components. However, these patents provide no suggestion as to how simultaneous doping of active devices and polysilicon components might be achieved when the resistance of the polysilicon must be controlled relatively precisely.